1. Field of the Invention
The present invention relates to a high-voltage integrated circuit (HVIC) that drives semiconductor elements connected in a half-bridge circuit and to a semiconductor element drive apparatus that is able to notify a low-side circuit of an abnormality in a high-side circuit via a level-shift circuit (a level-down circuit).
2. Background of the Related Art
An industrial motor, a power supply for a server, or the like is controlled by driving semiconductor elements connected in a half-bridge circuit. An HVIC is used as a control IC for driving these semiconductor elements. The HVIC includes a high-side circuit that controls semiconductor elements on the upper-level side of the half-bridge circuit and a low-side circuit that controls semiconductor elements on the lower-level side of the half-bridge circuit. Namely, the semiconductor elements on both the upper- and lower-level sides can be driven by a single IC. The HVIC outputs a signal for driving the semiconductor elements on the upper- and lower-level sides in response to a control signal from a microcomputer or the like. In particular, the HVIC includes a level-shift circuit for driving semiconductor elements on the upper-level side. Such a level-shift circuit is used for shifting a level of a control signal inputted with a low potential and transmitting the shifted signal to a high potential side.
The HVIC also includes a level-shift circuit (a level-down circuit). When an abnormality occurs in a high-side circuit, the level-shift circuit notifies a low-side circuit of the abnormality (for example, see Japanese Laid-open Patent Publication No. 08-330929 (paragraphs [0003] and [0012] and FIG. 1) and Japanese Laid-open Patent Publication No. 2004-304929 (paragraph [0021] and FIG. 2)).
A metal-oxide-semiconductor (MOS) gate driver circuit discussed in Japanese Laid-open Patent Publication No. 08-330929 includes a level-shift circuit. When an input that exceeds a value given to an external input terminal in a high-side circuit is given, the level-shift circuit notifies a low-side circuit of the input. This level-shift circuit includes a PMOS element. When an abnormality occurs in a high-side circuit, this PMOS element shifts a level of a signal indicating the abnormality. In this way, the signal indicating the abnormality in the high-side circuit is transmitted to the low-side circuit, and an error signal is outputted from an output terminal of the low-side circuit.
Japanese Laid-open Patent Publication No. 2004-304929 also discusses a gate drive circuit. When an abnormality is detected in a high-side circuit, a signal indicating the detection of the abnormality is transmitted to a low-side circuit via a level shift down circuit (a level-down circuit) including PMOS (p-channel metal-oxide-semiconductor field-effect transistor) and NMOS (n-channel metal-oxide-semiconductor field-effect transistor) elements and is outputted to the outside.
According to Japanese Laid-open Patent Publication No. 2004-304929, different types of abnormality, such as an overcurrent flowing through a semiconductor element in the high-side circuit and a drop of a control power supply voltage, can be transmitted to the low-side circuit. However, since signals indicating the different types of abnormality are transmitted by the level-down circuit in the same way, the low-side circuit cannot distinguish the types of abnormality signal transmitted.
There are known techniques directed to such cases in which different types of abnormality signal can be transmitted. According to these techniques, the different types of abnormality signal are distinguished from each other and transmitted differently. More specifically, an alarm signal corresponding to an individual type of abnormality signal is outputted (for example, see Japanese Laid-open Patent Publication No. 2012-10544 and Japanese Laid-open Patent Publication No. 2012-143125). These Japanese Laid-open Patent Publication No. 2012-10544 and Japanese Laid-open Patent Publication No. 2012-143125 discuss a semiconductor device drive circuit including a plurality of protection circuits. Different types of abnormality detected by the plurality of protection circuits are turned into pulse signals having different pulse widths corresponding to the respective protection circuits. In this way, the different types of abnormality detected are distinguished from each other and transmitted differently.
Next, an operation example of the HVIC will be described. In this example, different types of abnormality are detected in the high-side circuit of the HVIC, and the detection results are transmitted to the low-side circuit of the HVIC via a level-down circuit. In the following description, the name of an individual terminal and a voltage, signal, etc. at that terminal are denoted by the same reference character.
FIG. 10 illustrates an example of a configuration of a level-down circuit included in an HVIC. FIG. 11 illustrates functions of a pulse generation circuit. FIG. 12 is a time chart illustrating operations of the pulse generation circuit. FIG. 13 illustrates an output from the pulse generation unit.
As illustrated in FIG. 10, the HVIC includes a high-side circuit 100 and a low-side circuit 200. The HVIC includes a terminal VB via which a high-side power supply voltage VB, which is a main power supply of the high-side circuit 100, is applied to the high-side circuit 100, a terminal OH to which an overheat signal OH is inputted, a terminal OC to which an overcurrent signal OC is inputted, and a terminal VS to which a reference potential VS of the high-side circuit 100 is inputted. In addition, the HVIC includes a terminal VCC via which a low-side power supply voltage VCC, which is a main power supply of the low-side circuit 200, is applied to the low-side circuit 200, a terminal ALM to which an alarm signal ALM is outputted, and a terminal GND to which a reference potential GND of the low-side circuit 200 is inputted.
The high-side circuit 100 includes a control circuit 110 and PMOS elements (high-voltage P channel MOSFETs) PM1 and PM2. The control circuit 110 includes an overheat detection unit 111, a voltage drop detection unit 112, an overcurrent detection unit 113, an arbiter 114, and a pulse generation circuit 115. The overheat detection unit 111 receives the overheat signal OH and monitors an overheat status of a power semiconductor element. The voltage drop detection unit 112 receives the high-side power supply voltage VB and monitors a drop of the high-side power supply voltage VB. The overcurrent detection unit 113 receives the overcurrent signal OC and monitors an overcurrent status of the power semiconductor element. The arbiter 114 receives an overheat detection signal OHIN from the overheat detection unit 111, a voltage drop detection signal UVIN from the voltage drop detection unit 112, and an overcurrent detection signal OCIN from the overcurrent detection unit 113. The arbiter 114 performs an arbitration operation on these inputted signals and transmits arbitrated signals OHE, UVE, and OCE to the pulse generation circuit 115. The pulse generation circuit 115 controls the PMOS elements PM1 and PM2 by using pulse signals generated on the basis of these signals OHE, UVE, and OCE.
The PMOS elements PM1 and PM2 have drain terminals connected to the low-side circuit 200 and transmit an abnormality signal detected in the high-side circuit 100. The low-side circuit 200 includes a control circuit 210. This control circuit 210 includes a voltage conversion, in-phase noise filter, and pulse generation unit 211, a latch buffer 212, a detection and analysis unit 213, and an alarm output unit 214. The voltage conversion, in-phase noise filter, and pulse generation unit 211 converts an abnormality signal transmitted from the high-side circuit 100 into a voltage, filters in-phase noise, and generates pulses ER1 and ER2. The latch buffer 212 changes its state on the basis of the pulses ER1 and ER2 and outputs signals OHR and OCR. The detection and analysis unit 213 detects and analyzes the inputted signals OHR and OCR and outputs analysis result signals ERDT, OHER, OCER, UVER, and RXER to the alarm output unit 214. The alarm output unit 214 outputs an alarm signal ALM to the terminal ALM in response to these signals.
With this HVIC, when an abnormality such as an overheat, an overcurrent, or a voltage drop is detected in the high-side circuit 100, the pulse generation circuit 115 generates a pulse signal based on the type of the abnormality. This pulse signal is transmitted to the low-side circuit 200 by a level-down circuit including the PMOS elements PM1 and PM2 and the voltage conversion function of the voltage conversion, in-phase noise filter, and pulse generation unit 211. In this way, the low-side circuit 200 is notified of occurrence of an abnormality in the high-side circuit 100.
An outline of how the level-down circuit performs signal transmission will be described by using FIG. 11, which illustrates functions of the pulse generation circuit 115, and FIG. 12, which is a time chart illustrating operations of the pulse generation circuit 115.
FIGS. 11 and 12 illustrate how the pulse generation circuit 115 drives the level-down circuit on the high-side circuit 100 in response to an abnormality detected in the high-side circuit 100. More specifically, when an overcurrent (OC) abnormality is detected, the pulse generation circuit 115 generates a pulse only to the PMOS element PM2. When an overheat (OH) abnormality is detected, the pulse generation circuit 115 generates a pulse only to the PMOS element PM1. In addition, when a voltage drop (UV) abnormality is detected, the pulse generation circuit 115 alternately generates a pulse to the PMOS element PM1 and a pulse to the PMOS element PM2.
By changing the way of outputting a pulse to the level-down circuit in this way, abnormalities that occur in the high-side circuit 100 are distinguished. In the example in FIG. 12, when an abnormality is detected, a corresponding one of or both of the PMOS elements PM1 and PM2 are intermittently operated. This is because continuously maintaining a PMOS element in an on-state causes a current to continuously flow, which is not preferable from a viewpoint of energy saving.
The pulse generation circuit 115 includes a pulse generation unit, which outputs a clock pulse CLK whose period and frequency are constant irrespective of the high-side power supply voltage VB, as illustrated in FIG. 13.
The clock pulse CLK outputted from the pulse generation unit in the conventional HVIC has a constant pulse period and frequency irrespective of change of the high-side power supply voltage VB. However, when the high-side power supply voltage VB drops and when the pulse generation circuit 115 notifies the level-down circuit of voltage drop abnormality signal UVE, the gate voltage (ΔVgs) of a PMOS element arranged on the high side of the level-down circuit is dropped along with the drop of the high-side power supply voltage VB. Consequently, a current (the drain current of the PMOS element) supplied to the low side when an individual PMOS element is brought in an on-state is decreased. Namely, when the high-side power supply voltage VB is dropped by a certain degree, the pulse period of the clock pulse CLK cannot supply a sufficient amount of charges for changing the signal on the low side. Thus, there is a problem that proper signal transmission to the low side cannot be performed.